2D-NAND flash is impressive due to its extremely fast access times, low latencies, energy efficiency, robustness, and small form factors. The greatest technical advances were aimed at reducing costs through structural downsizing. However, a physical limit has now been reached at 15 nanometers. Even smaller structures would lead to more errors when reading out data and to endurance and data retention being reduced - ultimately the long-term "integrity" of the data would not be guaranteed. Innovations are, therefore, going in the direction of three-dimensional NAND (3D-NAND) and increasing the number of bits on a cell.
Current solutions: Charge trapping and floating gate
With a 3D-NAND flash memory, multiple layers of flash cells are stacked - similar to a high-rise building, thereby enhancing the capacity significantly. A simple comparison, but the technology behind it is far more complex. Today, two approaches have become standard: Floating gate and charge trap. Although they differ completely in the way they are manufactured, the idea is similar. With the floating gate method, the charges are stored with a floating gate on an electronically isolated gate between the channel and the control gate. In the charge trap approach, on the other hand, the charges are held at trapping centers, a silicon nitride layer that is separated from the channel by a thin tunnel oxide layer. In both cases, the defined CG layers are selected via the lines of the control gate or the wordline (WL). The string is selected via bitlines (BLs).
The 3D-NAND memory technology offers numerous advantages for suppliers and customers alike. The higher memory density ensures that flash suppliers can produce greater capacities and more gigabytes per silicon wafer at similar rates of yield. Customers benefit from a noticeable reduction in price while enjoying the same shelf life.
However, a supplier has yet to unveil a 3D-NAND product with high temperature resistance, as is often required in industry. The first 3D-NAND products that are suitable for industrial temperatures should be launched in 2019.
QLC NAND flash
Increased memory density is not only achieved by stacking memory cells but also by increasing the capacity of the actual cells. When NAND technology was first introduced, only the single level cell (SLC) architecture was available. In other words, one bit could be stored per memory cell. The multi-level cell (MLC) and the triple level cell (TLC), which can store two or three bits respectively, were subsequently added. Now, QLC NAND flash, the next generation of 3D-NAND architectures, is just around the corner. QLC stands for "quadruple level cell" or "quad level cell" and thus for four bits per cell. This architecture currently enables up to 96 layers. The fourth generation from Micron and the fifth generation from Samsung, SK Hynix, and Toshiba should allow up to 128 layers.
More capacity, lower shelf life
The major advantage of the QLC flash is the considerably higher memory density and thus greater capacity. As a result, smaller footprints are possible, data racks can be up to 7.7x smaller than when using HDDs, thereby saving valuable space in data centers.
Nonetheless, the QLC architecture also displays certain weaknesses. There are 16 different voltages per memory cell, which makes writing data a more complex and slower task. Furthermore, the reliability of the memory decreases. The validation of individual bits is more demanding and the cells degrade over several write cycles, making it difficult to determine individual bit values. This may result in data errors. ECC (error correction code) is helpful in this case but not sufficient to compensate for this effect. This also negatively impacts the shelf life of the QLC memories: With 500 to 1,500 P/E cycles (program/erase, write and erase cycles), it is significantly lower than with a 3D-TLC architecture and substantially lower than with an SLC architecture.
Ready for big data applications
Nevertheless, the use of QLC flash is recommendable in many areas of application. Due to the low P/E cycles, the memories are primarily designed for read operations (90%+). QLC memories can be used wherever large amounts of data need to be read quickly, but only a few write processes are required. This includes, for example, real-time analyses of big data, data inputs for artificial intelligences, the provision of media for on-demand services, NoSQL databases, and user authentication. For these types of application, the TCO (total cost of ownership) is also significantly lower than with HDDs, as the total number of memory units required is much lower, less power is consumed, and more IOPS are processed. Due to the high memory density, applications in the embedded and mobile market are also conceivable.
5210 ION: The first QLC-SSD
In cooperation with Intel, Micron has launched the first product with QLC: The Enterprise SSD series 5210 ION, which is based on SATA. The SSD uses four bits per cell with a total of 64 cell layers. Between 1.92 and 7.68 terabytes can be stored on just 2.5 inches. The sequential data rates are about 500Mbps for reading and 340Mbps for writing. The 5210 ION series is basically designed to meet the demands of reading-intensive clouds. #
With the third generation of 3D-NAND memories that is still under development, Micron wants to offer the highest density of gigabit per millimeter with a total of 96 layers. Other suppliers will soon also be in a position to launch their first QLC solutions: Intel, which now develops its own 3D-NAND memory independently of Micron, recently announced the production of the first PCIe-based QLC SSD and Toshiba Memory plans to start mass production of the BiCS4 QLC NAND in 2019. As a partner of Apcacer, Intel, Swissbit, Toshiba, Transcend, and Wilk, Rutronik is in close contact with the leading suppliers of data memories. The Rutronik Storage Team provides developers and purchasers with comprehensive support and advice when selecting the right memory technology.
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